1. Field of the Invention
The present invention relates to a memory controller for controlling access to a flash memory in which stored data is erased in units of physical blocks each consisting of a plurality of memory cells, a flash memory system with the memory controller, and a control method of the flash memory.
2. Related Background Art
In recent years, flash memories, particularly, NAND type flash memories are popularly used as semiconductor memories used in memory systems such as memory cards and silicon disks. In a storage device using this NAND type flash memory, it is necessary to accurately administer a correspondence relation between logical addresses supplied by a host system and physical addresses in the flash memory. For this reason, it is common practice to write, for example, in a redundant region of a physical block, logical address information indicating a scope of logical addresses corresponding to data written in the physical block.
For updating data stored in this NAND type flash memory, new data is written into another physical block in which stored data is erased, and stored data in a physical block storing old data is erased. In certain cases, however, the stored data is not immediately erased from the physical block storing the old data, but the physical block storing the old data coexists with the physical block storing the new data. In such cases, there exist a plurality of physical blocks in which the same logical address information is written in their redundant region, and it is thus necessary to judge a chronological relation of data stored in these physical blocks.
In this connection, Patent Document 1 describes the technology of writing chronological identification information indicating a chronological relation of data stored in physical blocks, together with the logical address information, in the redundant regions of the physical blocks. This chronological identification information used is cyclic numbers that go back to the first number in a predetermined cycle. [Patent Document 1] Japanese Patent Application 2005-190288
In the conventional technology described above, however, a difference can be large between a cyclic number written in a physical block storing old data and a cyclic number written in a physical block storing new data, and in this case it becomes infeasible to determine the chronological relation on the basis of the cyclic numbers. For example, let us explain a case using cyclic numbers starting from 0 and returning to 0 after 15. In this setting, supposing there are a physical block in which 12 is written as a cyclic number and a physical block in which 13 is written as a cyclic number, one might add a physical block in which 14 is written as a cyclic number, and erase stored data in the physical block in which 13 is written as a cyclic number. Then one might add a physical block in which 15 is written as a cyclic number and erase stored data in the physical block in which 14 is written as a cyclic number. Subsequently, one might add a physical block in which 0 is written as a cyclic number and erase stored data in the physical block in which 15 is written as a cyclic number. As such processes are repeated to leave the physical block in which 12 is written as a cyclic number and a physical block in which 4 is written as a cyclic number, the number of steps from 12 to 4 (number of stages with advances of cyclic numbers according to a cycle order) becomes equal to the number of steps from 4 to 12, and it becomes infeasible to determine the chronological relation on the basis of the cyclic numbers.
An object of the present invention is therefore to provide a memory controller capable of, when there are a plurality of physical blocks storing data with an identical scope of logical addresses in a flash memory as a target of access, accurately determining a chronological relation thereof, a flash memory system provided with the memory controller, and a control method of the flash memory.